Managed By:

Joint Venture of DSIIDC, An undertaking of Delhi Govt. & TCIL, A Govt. of India Enterprise Under Ministry of Communications & Information Technology

VLSI Training

TCIL-IT Chandigarh is swiftly becoming a leading and valuable learning center that provides training courses in IT and electronic domains. Networks are the most complicated array of systems and devices and TCIL-IT Chandigarh is positioned to safeguard and streamline the integrity of these networks.

The engineering colleges and universities lag behind in imparting precise knowledge and training on VLSI as per the needs of the industry. This creates gap amid the fresh engineering students and the industry. TCIL-IT Chandigarh has its programs and training courses structured in way that it bridges this gap and provides particular VLSI training knowledge together with personal skill and advanced technical development.

Our program is designed by industry experts that excel in the field of VLSI, having decades of experience in working with some latest tools and techniques of VLSI. Some main highlights of our training course cover:

• Verilog coding techniques
• Advanced digital design
• On-chip architecture exploration
• Routing, placement and floor planning
• Static and synthesis timing analysis

So if you wish to be one amongst the individuals who have set themselves at a high profile in multi-national networking companies, then call us. TCIL-IT Chandigarh will help you accomplish all your dreams true. We enable you with practical knowledge in VLSI so that you climb the success ladder easily.

We offer the following modules of VLSI training in Chandigarh
CMOS

  • MOS Fundamentals and Characterization
  • NMOS/PMOS/CMOS Technologies
  • Fabrication Principles
  • Different Styles of Fabrication for NMOS/PMOS/CMOS
  • Design with CMOS Gates
  • Characterization of CMOS Circuits
  • Layout Representation for CMOS Circuits
  • Design Exercise using CMOS
  • Scaling Effects
  • Sub-Micron Designs
  • Parasitic Extraction and Calculations
  • Subsystem Design
  • Introduction of IC Design
  • Different Methodologies for IC Design
  • Fabrication Flows and Fundamentals

VHDL

  • VHDL Overview and Concepts
  • Levels of Abstraction
  • Entity, Architecture
  • Data Types and declaration
  • Enumerated Data Types
  • Relational, Logical, Arithmetic Operators
  • Signal and Variables, Constants
  • Process Statement
  • Concurrent Statements
  • When-else, With-select
  • Sequential Statement
  • If-then-else, Case
  • Slicing and Concatenation
  • Loop Statements
  • Delta Delay Concept
  • Arrays, Memory Modeling, FSM
  • Writing Procedures
  • Writing Functions
  • Behavioral / RTL Coding
  • Operator Overloading
  • Structural Coding
  • Component declarations and installations
  • Generate Statement
  • Configuration Block
  • Libraries, Standard packages
  • Local and Global Declarations
  • Package, Package body
  • Writing Test Benches
  • Assertion based verification
  • Files read and write operations
  • Code for complex FPGA and ASICs
  • Generics and Generic maps

VERILOG

  • Language introduction
  • Levels of abstraction
  • Module, Ports types and declarations
  • Different Styles of Fabrication for NMOS/PMOS/CMOS
  • Registers and nets, Arrays
  • Identifiers, Parameters
  • Relational, Arithmetic, Logical, Bit-wise shift Operators
  • Writing expressions
  • Behavioral Modeling
  • Structural Coding
  • Continuous Assignments
  • Procedural Statements
  • Always, Initial Blocks, begin ebd, fork join
  • Blocking and Non-blocking statements
  • Operation Control Statements
  • If, case
  • Loops: while, for-loop, for-each, repeat
  • Combination and sequential circuit designs
  • CMOS gate modeling
  • Writing Tasks
  • Writing Functions
  • Compiler directives
  • Conditional Compilation
  • System Tasks
  • Gate level primitives
  • User defined primitives
  • Delays, Specify block
  • Testbenchs, modeling, timing checks
  • Assertion based verification
  • Code for synthesis
  • Advanced topics
  • Writing reusable code

System Verilog

  • Introduction to System Verilog
  • System Verilog Declaration spaces
  • System Verilog Literal Values and Built-in Data Types
  • System Verilog User-Defined and Enumerated Types
  • System Verilog Arrays, Structures and Unions
  • System Verilog Procedural Blocks, Tasks and Function
  • System Verilog Procedural Statements
  • Modelling Finite State Machines with System Verilog
  • System Verilog Design Hierarchy
  • System Verilog Interfaces
  • Behavioral and Transaction Level Modelling

FPGA Flow

  • Re-configurable Devices, FPGA’s/CPLD’s
  • Architectures of XILINX, ALTERA Devices
  • Designing with FPGAs
  • FPGA’s and its Design Flows
  • Architecture based coding
  • Efficient resource utilization
  • Constrains based synthesis
  • False paths and multi cycle paths
  • UCF file creation
  • Timing analysis/Floor Planning
  • Place and route/RPM
  • Back annotation, Gate level simulation, SDF Format
  • DSP on FPGA
  • Writing Scripts
  • Hands on experience with industry Standard Tools

ASIC Flow

Projects: As a part of course 2 mini projects and 1 major project

  • EDA Tools / CAD Flow for IC Design
  • Simulation/Synthesis using ASIC libraries
  • Clock Tree Synthesis
  • False paths / Multi cycle paths / Critical paths
  • Design for Testability (DFT)
  • Scan Insertion / Types of Scan
  • Fault Models
  • Logic BIST, Memory BIST, ATGP, Boundary Scan
  • Pattern Compression
  • Scan Diagnostics
  • Layout Design
  • Placing and Routing
  • LVS/DRC/OPC/Physical verification
  • Diagnosis, DFM, Yield Analysis
  • SOC Design and Trade-offs
  • Future Trends and challenges
  • ASIC Case Studies

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